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| LCX037BLT 3.4cm (1.35 Type) Black-and-White LCD Panel Description The LCX037BLT is a 3.4cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with a built-in peripheral driving circuit. Use of three LCX037BLT panels provides a full-color representation. The striped arrangement suitable for data display is capable of displaying fine text and vertical lines. The adoption of a new developed dot-line inverse drive system, CMP (Chemical Mechanical Polish) and OCS (On Chip Spacer) structures contribute to high picture quality. This panel has a polysilicon TFT high-speed scanner and built-in function to display images up/down and/or right/left inverse. The built-in 5V interface circuit leads to lower voltage of timing and control signals. Features * Number of active dots: 1,049,088 (1.35 Type, 3.4cm in diagonal) * High optical transmittance: 16% (typ.) * Dot-line inverse drive circuit * OCS structure * CMP (Chemical Mechanical Polish) structure * High contrast ratio with normally white mode: 300 (typ.) * Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible) * Up/down and/or right/left inverse display function * Antidust glass package Element Structure * Dots: 1366 (H) x 768 (V) = 1,049,088 * Built-in peripheral driver using polycrystalline silicon super thin film transistors Applications * Liquid crystal data projectors * Liquid crystal multimedia projectors * Liquid crystal rear-projector TVs, etc. The company's name and product's name in this data sheet is a trademark or a registered trademark of each company. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E00231-PS COM PAD 34 Block Diagram COM PAD VCOM SOUT VVDD VSS PST DWN VST VCK ENB Input Signal Level Shifter Circuit Up/Down and/or Right/Left Inversion Control Circuit V Shift Register 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 COML VSS HCK2 HCK1 HST RGT HVDD H Shift Register P Shift Register -2- V Shift Register COM PAD SIG12 SIG11 SIG10 SIG9 SIG8 SIG7 SIG6 SIG5 SIG4 SIG3 8 7 6 5 4 3 2 1 18 17 16 15 14 13 12 11 10 9 SIG2 SIG1 COMR PSIG4 PSIG3 PSIG2 PSIG1 VSSG COM PAD LCX037BLT LCX037BLT Absolute Maximum Ratings (VSS = 0V) * H driver supply voltage HVDD * V driver supply voltage VVDD * Common pad voltage COM, COML, COMR * H shift register input pin voltage HST, HCK1, HCK2, RGT * V shift register input pin voltage VST, VCK, PST, ENB, DWN * Video signal input pin voltage SIG1 to 12, PSIG1 to 4 * Operating temperature Topr * Storage temperature Tstg Panel temperature inside the antidust glass -1.0 to +20 -1.0 to +20 -1.0 to +17 -1.0 to +17 -1.0 to +17 -1.0 to +15 -10 to +70 -30 to +85 V V V V V V C C Operating Conditions (VSS = 0V) * Supply voltage HVDD 15.5 0.3V VVDD 15.5 0.3V * Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal) Vin 5.0 0.5V -3- LCX037BLT Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol VSSG PSIG1 PSIG2 PSIG3 PSIG4 COMR SIG1 SIG2 SIG3 SIG4 SIG5 SIG6 SIG7 SIG8 SIG9 SIG10 SIG11 SIG12 HVDD RGT HST HCK1 HCK2 VSS COML ENB VCK VST DWN PST VSS VVDD SOUT VCOM GND for V gate Uniformity improvement signal (for black) Uniformity improvement signal (for black) Uniformity improvement signal (for gray) Uniformity improvement signal (for gray) Voltage for right CS (Storage capacity) electrode line Video signal 1 to panel Video signal 2 to panel Video signal 3 to panel Video signal 4 to panel Video signal 5 to panel Video signal 6 to panel Video signal 7 to panel Video signal 8 to panel Video signal 9 to panel Video signal 10 to panel Video signal 11 to panel Video signal 12 to panel Power supply for H driver Drive direction pulse for H shift register (H: normal, L: reverse) Start pulse for H shift register drive Clock pulse for H shift register drive 1 Clock pulse for H shift register drive 2 GND (H, V, drivers) Voltage for left CS (storage capacity) electrode line Enable pulse for gate selection Clock pulse for V shift register drive Start pulse for V shift register drive Drive direction pulse for V shift register (H: normal, L: reverse) Start pulse for P shift register drive GND (H, V, P drivers) Power supply for V, P drivers Test pin; leave this pin open. Common voltage of panel -4- Description LCX037BLT Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a high resistor of 1M (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.) (1) VSIG1 to VSIG12, PSIG HVDD Input 1M (2) HCK1, HCK2 HVDD 250 Input 250 1M 250 Signal line Level conversion circuit (2-phase input) 250 1M Level conversion circuit (2-phase input) (3) RGT HVDD 2.5k Input 1M 2.5k Level conversion circuit (single-phase input) (4) HST HVDD 250 Input 1M 250 Level conversion circuit (single-phase input) (5) PST, VCK VVDD 250 Input 1M 250 Level conversion circuit (single-phase input) (6) VST, ENB, DWN VVDD 2.5k Input 1M 2.5k Level conversion circuit (single-phase input) (7) VCOM, COML, COMR VVDD Input 1M LC (8) HVDD, VSSG, VVDD Input 1M are all Vss. -5- LCX037BLT Input Signals 1. Input signal voltage conditions (VSS = 0V) Item H shift register input voltage (Low) HST, HCK1, HCK2, RGT (High) V shift register input voltage (Low) VB1, VB2, BLK, VST, VCK, PCG, ENB, DWN (High) Video signal center voltage Video signal input range1 Common voltage of panel2 Uniformity improvement signal input voltage3 1 2 Symbol VHIL VHIH VVIL VVIH VVC Vsig1, 3, 5, 7, 9, 11 Vsig2, 4, 6, 8 Vcom Vpsig1, 3 Vpsig2, 4 Min. -0.5 4.5 -0.5 4.5 7.4 VVC 4.4 VVC 4.4 VVC - 0.8 VVC 4.4 VVC 2.3 Typ. 0.0 5.0 0.0 5.0 7.5 VVC 4.5 VVC 4.5 VVC - 0.7 VVC 4.5 VVC 2.5 Max. 0.4 5.5 0.4 5.5 7.6 VVC 4.6 VVC 4.6 VVC - 0.6 VVC 4.6 VVC 2.7 Unit V V V V V V V V V V Input video signal shall be symmetrical to VVC. The typical value of the common pad voltage may lower its suitable voltage according to the set construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the typical value is lowered, the maximum and minimum values may lower. -6- LCX037BLT 3 Input video signal, and a uniformity improvement signal as shown phase like below. And the rise time trPsig and the fall time tfPsig of Psig1 to 4 are suppressed within 400ns. Phase relationship between video signal and uniformity improvement signal H blanking period H effective period Vsig1, 3, 5, 7, 9, 11 Sig1, 3, 5, 7, 9, 11 Sig-Center Time Vpsig1, 4 Psig1 Psig4 Sig-Center Psig4 Psig1 Time Vsig2, 4, 6, 8, 10, 12 Sig-Center Sig2, 4, 6, 8, 10, 12 Time Vpsig2, 3 Psig2 Psig3 Psig3 Sig-Center Psig2 Time Level Conversion Circuit The LCX037BLT has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 0.5V. -7- LCX037BLT 2. Clock timing conditions (Ta = 25C) Item Hst rise time HST Hst fall time Hst data set-up time Hst data hold time Hckn rise time4 HCK Hckn fall time4 Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVck tfVck trEnb tfEnb tdEnb twEnb toEnb toPst trPst tfPst tdPst thPst toHst (fHckn = 6.67MHz, fVck = 25.6kHz, fv = 60Hz) Min. -- -- -10 65 -- -- -15 -15 -- -- 5 5 -- -- -- -- 8005 900 300 390 -- -- -10 65 -- Typ. -- -- 0 75 -- -- 0 0 -- -- 10 10 -- -- -- -- 1000 1000 400 400 -- -- 0 75 4 Max. 30 30 10 85 30 30 15 15 100 100 15 15 100 100 100 100 1200 1100 500 410 30 30 10 85 -- x4 cycles of Hck ns s ns Unit Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Vst rise time VST Vst fall time Vst data set-up time Vst data hold time VCK Vck rise time Vck fall time Enb rise time Enb fall time ENB Horizontal video period completed to Enb fall time Enb width Vck rise/fall to Enb rise time Enb rise to Pst rise time Pst rise time Pst fall time PST Pst data set-up time Pst data hold time Pst rise to Hst rise time 4 5 Hckn means Hck1 and Hck2. The minimum value of tdEnb is 800ns. When H-BLK has a long period and has some time to spare, take more time prior to other value. -8- LCX037BLT Hst 10% trHst Waveform 90% 90% 10% tfHst Conditions * Hckn4 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tfHst 6 Hst data set-up time tdHst 50% 50% Hst Hck1 Hst data hold time thHst tdHst 50% 50% thHst 90% 10% * Hckn4 duty cycle 50% to1Hck = 0ns to2Hck = 0ns Hckn rise time4 trHckn 90% 4 Hckn 10% Hckn fall time4 HCK Hck1 fall to Hck2 rise time tfHckn 6 to1Hck Hck1 * Hckn4 duty cycle 50% to1Hck = 0ns to2Hck = 0ns trHckn tfHckn 50% 50% 50% 50% Hck1 rise to Hck2 fall time to2Hck Hck2 to2Hck to1Hck 6 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means -. The black dot at an arrow ( ) indicates the start of measurement. -9- LCX037BLT Vst 10% trVst 6 Waveform 90% 90% 10% tfVst Conditions tfVst Vst data set-up time tdVst 50% Vst 50% 50% 50% Vck Vst data hold time thVst tdVst 90% thVst 90% 10% Vck rise time VCK Vck fall time trVck Vck 10% tfVck trVckn tfVckn Enb rise time trEnb Enb 90% 10% 10% 90% Enb fall time Horizontal video period completed to Enb fall time ENB Enb width Vck rise/fall to Enb fall time Enb rise to Pst rise time tfEnb 6 H video period tfEnb trEnb tdEnb H blanking period twEnb twEnb Enb tdEnb 50% 50% 50% toEnb Pst toPst 50% toEnb Vck toPst - 10 - LCX037BLT Item Pst rise time Symbol trPst Pst 10% Waveform 90% 90% 10% tfPst Conditions Pst fall time tfPst trPst Pst data set-up time tdPst Pst 50% 50% 50% 50% HCKn PST Pst data set-up time thPst tdPst thPst 6 Pst 50% toPst 50% Pst rise to Hst rise time toHst Hst Hckn 1 2 3 4 - 11 - LCX037BLT Electrical Characteristics (Ta = 25C, HVDD = 15.5V, VVDD = 15.5V) 1. Horizontal drivers Item Input pin capacitance HCKn HST Input pin current HCK1 HCK2 HST RGT Video signal input pin capacitance Current consumption Csig IH Symbol CHckn CHst Min. -- -- Typ. 15 15 Max. 20 20 -- -- -- -- 250 25 Unit pF pF A A A A pF mA HCKn: HCK1, HCK2 (6.67MHz) HCK1 = GND HCK2 = GND HST = GND RGT = GND Condition -1000 -500 -1000 -500 -500 -150 -- -- -170 -40 180 15 2. Vertical drivers Item Input pin capacitance VCK VST, PST Input pin current VST, ENB, DWN Current consumption IV VCK, PST Symbol CVck CVst Min. -- -- -500 -150 -- Typ. 15 15 -150 -35 20 Max. 20 20 -- -- 30 Unit pF pF A A mA VCK = GND, PST = GND VST, ENB, DWN = GND VCK: (25.6kHz) Condition 3. Total power consumption of the panel Item Symbol Min. -- Typ. 550 Max. 1000 Unit mW Total power consumption of the panel PWR 4. Pin input resistance Item Pin - VSS input resistance Symbol Rpin Min. 0.4 Typ. 1 Max. -- Unit M 5. Uniformity improvement signal Item Symbol Min. -- Typ. 0.5 Max. 5.0 Unit nF Input pin capacitance for uniformity CPSIG1 improvement signal to 4 - 12 - LCX037BLT Electro-optical Characteristics Item Contrast ratio Optical transmittance 25C 25C Symbol Measurement method Min. CR T RV90-25 25C V90 60C GV90-25 BV90-25 RV90-60 GV90-60 BV90-60 RV50-25 25C V-T characteristics V50 60C GV50-25 BV50-25 RV50-60 GV50-60 BV50-60 RV10-25 25C V10 60C GV10-25 BV10-25 RV10-60 GV10-60 BV10-60 ON time Response time OFF time Flicker Image retention time Cross talk 0C 25C 0C 25C 60C 25C 25C ton0 ton25 toff0 toff25 F YT60 CTK 5 6 7 4 3 1 2 200 13 0.9 1.0 1.2 0.9 1.0 1.1 1.3 1.4 1.5 1.2 1.3 1.4 1.7 1.8 1.9 1.7 1.8 1.8 -- -- -- -- -- -- -- Typ. 300 16 1.3 1.4 1.6 1.3 1.4 1.5 1.7 1.8 1.9 1.6 1.7 1.8 2.1 2.2 2.3 2.1 2.2 2.2 24.0 9.0 99.0 27.0 Max. -- -- 1.6 1.7 1.9 1.6 1.7 1.8 2.0 2.1 2.2 1.9 2.0 2.1 2.4 2.5 2.6 2.4 2.5 2.5 80.0 40.0 200.0 70.0 dB s % ms V Unit -- % -82.0 -40.0 0 -- -- 5 Reflection Preventive Processing When a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. This prevents characteristic deterioration caused by luminous reflection. - 13 - LCX037BLT Approx. 2000mm Screen Luminance Meter LCD Projector Measurement Equipment Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or equivalent Projection lens: Focal distance 80mm, F1.9 Light source: 155W metal Haloid arc lamp (Color temperature 7500K 500) (x24, Sensor area: 7mm) Polarizer: Side of incidence-Nitto Denko's EG-1224DU or Polatechno's SKN-18242T Side of output light-Polatechno's SHC-128 or equivalent * Measurement system II Optical fiber Light receptor lens Light Detector Measurement Equipment Drive Circuit LCD panel Light Source 1. Contrast Ratio Contrast Ratio (CR) is given by the following formula (1). CR = L (White) ... (1) L (Black) L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the center of the screen at VAC = 5.5V. Both luminosities are measured by System I. - 14 - LCX037BLT 2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). T= White luminance Luminance of light source x 100 [%] ... (2) "White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V on Measurement System I. Transmittance [%] 3. V-T Characteristics V-T characteristics, or the relationship between signal amplitude and the transmittance of the panels, are measured by System II by inputting the same signal amplitude VAC to each input pin. V90, V50, and V10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively. 90 50 10 V90 V50 V10 VAC - Signal amplitude [V] 4. Response Time Response time ton and toff are defined by formulas (5) and (6) respectively. ton = t1 - tON ...(5) toff = t2 - tOFF ...(6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure. Input signal voltage (Waveform applied to the measured pixels) 4.5V 7.0V 0.5V 0V Optical transmittance output waveform 100% 90% 10% 0% tON t1 ton tOFF t2 toff - 15 - LCX037BLT 5. Flicker Flicker (F) is given by formula (7). DC and AC (SXGA: 30Hz, rms) components of the panel output signal for gray raster mode are measured by a DC voltmeter and a spectrum analyzer in System II. F [dB] = 20log { AC component } ...(7) DC component Each input signal voltage for gray raster mode is given by Vsig = 7.0 V50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics. 6. Image Retention Time Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 7.5 VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention, measure the time till the residual image becomes indistinct. Monoscope signal conditions: Vsig = 7.5 4.5 or 2.0 [V] (shown in the right figure) Vcom = 6.8V Black level 5.5V 2.0V 7.5V 2.0V 5.5V White level 0V Vsig waveform 7. Cross Talk Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi (i = 1 to 4) around a black window (Vsig = 4.5 V/1V). Cross talk value CTK = W2 W2' W3 W3' W1 W1' W4 W4' Wi' - Wi x 100 [%] Wi - 16 - LCX037BLT Viewing angle characteristics (Typical Value) 90 CR = 5 10 20 50 100 180 150 250 200 10 30 50 70 0 Theta Phi 270 0 Z 90 Marking 180 Y 0 X 270 Measurement method - 17 - LCX037BLT Optical transmittance of LCD panel (Typical Value) 30 20 Trans. [%] 10 0 400 500 Wavelength [nm] 600 700 Measurement method: Measurement system II - 18 - 1. Dot Arrangement The dots are arranged in a stripe. The shaded area is used for the dark border around the display. (TFT substrate view from com pad) (Upper) Gate SW Video 1 2 3 3 4 2 4 5 1 6 5 6 Gate SW Gate SW Gate SW Gate SW (Right) Gate SW (Left) Gate: D1st D1 D1 D1 D1 Gate: 1st 1 D1 1 D1 1 D1 1 D1 1 D1 Gate: 2nd 2 1 1 2 1 1 2 1 2 6 dots 6 dots 1 dot 1366 dots (Lower) 1 dots 6 dots 6 dots D1 : Pixel of transistor open and close at the D1st gate Down scan: For video 1 , Up scan: For video 2 , 1 : Pixel of transistor open and close at the 1st gate 2 : Pixel of transistor open and close at the 2nd gate 4, : LCX037BLT 767 : Pixel of transistor open and close at the 767th gate 2 dots - 19 - Active area 2 2 2 2 767 767 767 767 768 767 768 767 768 767 767 768 767 768 768 768 768 767 Gate: 767th Gate: 768th 768 dots Photo-Shielding 2 dots LCX037BLT 2. LCD Panel Operations [Description of basic operations] * To perform dot-line inverse drive, the pixel arrangement of the same gate is as shown in the diagram. Therefore, the input signal matched to respective orrangement is requied for input signals SIG1 to 12. * A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 768 gate lines sequentially in a single horizontal scanning period. * A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits, applies selected pulses to every 1366 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines. * Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn on to apply a video signal to the dot. The same procedures lead to the entire 1366 x 768 dots to display a picture in a single vertical scanning period. - 20 - LCX037BLT This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting systems. * Right/left inverse mode * Up/down inverse mode These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are shown below. RGT H L Mode Right scan Left scan DWN H L Mode Down scan Up scan Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin block upside. To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for the H system must be varied. The phase relationship between the start pulse and the clock for each mode is shown below. Vertical direction display period (DWN = H) VST Gate name VCK D1 1 2 3 4 765 766 767 768 V effective display period 768H Vertical direction display period (DWN = L) VST Gate name VCK 768 767 766 765 4 3 2 1 D1 V effective display period 768H Horizontal direction display period (RGT = H) PST HST HCK1 1 2 3 4 225 226 227 228 D1 D2 HCK2 H display period 228V Horizontal direction display period (RGT = L) PST HST HCK1 228 227 226 225 4 3 2 1 HCK2 D1 D2 H display period 228V - 21 - LCX037BLT 3. 12-dot Simultaneous Sampling The horizontal shift register samples signals VSIG1 to VSIG6, VSIG7 to VSIG12 simultaneously. This requires phase matching between signals VSIG1 to VSIG12 to prevent the horizontal resolution from deteriorating. Thus, phase matching between each signal is required using an external signal delaying circuit before applying the video signal to the LCD panel. The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following phase relationship diagram indicates the phase setting for right scan (RGT = High). For left scan (RGT = Low), the phase settings for signals VSIG1 to VSIG12 are exactly reversed. VSIG1 S/H CK1 S/H 7 VSIG1 VSIG2 S/H CK2 S/H 8 VSIG2 VSIG3 S/H CK3 S/H 9 VSIG3 VSIG4 S/H CK4 S/H 10 VSIG4 VSIG5 S/H CK5 S/H 11 VSIG5 VSIG6 S/H CK6 12 VSIG6 VSIG7 S/H CK7 S/H 13 VSIG7 VSIG8 S/H CK8 S/H 14 VSIG8 VSIG9 S/H CK9 S/H 15 VSIG9 VSIG10 S/H CK10 S/H 16 VSIG10 VSIG11 S/H CK11 S/H 17 VSIG11 VSIG12 S/H CK12 18 VSIG12 - 22 - LCX037BLT LCX037BLT HCKn CK1 CK2 CK3 CK4 CK5 CK6 CK7 CK8 CK9 CK10 CK11 CK12 Display System Block Diagram An example of display system is shown below. D/A CXA3197R S/H Driver CXA3512R 6 LCX037 Digital Signal Driver R-IN 16 G-IN 16 B-IN 16 VSYNC HSYNC CXD2467Q 60 CXD3504R 60 Selection-type Delay Line 6 CXA3197R CXA3512R CXA3197R CXA3512R 6 LCX037 6 CXA3197R CXA3512R CXA3197R CXA3512R 6 LCX037 1/2 CXA3197R MCK X'tal CXA3512R 6 FRP, PRG, ENB - 23 - Timing Pulse LCX037BLT Notes on Handling (1) Static charge prevention Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mats on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in a clean environment. b) When delivered, the panel surface (glass panel) is covered by a protective sheet. Peel off the protective sheet carefully so as not to damage the glass panel. c) Do not touch the glass panel surface. The surface is easily scratched. When cleaning, use a cleanroom wiper with isopropyl alcohol. Be careful not to leave a stain on the surface. d) Use ionized air to blow dust off the glass panel. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop the panel. c) Do not twist or bend the panel or panel frame. d) Keep the panel away from heat sources. e) Do not dampen the panel with water or other solvents. f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel damages. g) Minimum radius of bending curvature for a flexible substrate must be 1mm. h) Torque required to tighten screws on a panel must be 3kg * cm or less. i) Use appropriate filter to protect a panel. j) Do not pressure the portion other than mounting hole (cover). - 24 - LCX037BLT Package Outline Unit: mm 17.5 0.05 4.9 0.1 0.3 0.05 2.2 0.1 Thickness of the connector 4 (62.6) 1 2.5 4-R Incident light Polarizing Axis 3-2.3 0.05 2 3 5 34.0 0.1 39.0 0.15 101.5 1.4 6 7 Incident light 8 Output light Polarizing Axis Active Area 9 2.1 0.05 (30.05) 30.0 0.1 42.0 0.15 18.0 0.15 2.5 0.1 2.1 0.05 (16.90) 21.0 0.15 6.0 0.1 No 1 0.5 0.15 4.0 0.3 Description FPC Molding material Outside frame Reinforcing board 2 3 4 P 0.5 0.02 x 33 = 16.5 0.03 0.5 0.1 0.35 0.03 PIN1 PIN34 5 Reinforcing material 6 7 electrode (enlarged) The rotation angle of the active area relative to H and V is 1. 8 9 Glass 1 Glass 2 Cover 1 Cover 2 weight 13.7g - 25 - |
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